For example, Japanese Unexamined Patent Application Publication No. 2003-309193 (Patent Document 1) discloses a non-volatile memory cell transistor having a first gate electrode (control gate electrode) and a second gate electrode (memory gate electrode) disposed via an insulating film and a charge accumulating region, and the memory cell transistor is processed to have a structure in which the height of the first gate electrode from the surface of a substrate is lower than the height of the second gate electrode from the surface of the substrate or the height of a gate electrode of a transistor formed in a peripheral circuit from the surface of the substrate.
Also, Japanese Unexamined Patent Application Publication No. 2006-54292 (Patent Document 2) discloses a method in which an isolated auxiliary pattern adjacent to a selection gate electrode is disposed in a memory cell having a split gate structure, and the gap therebetween is filled with polysilicon of a sidewall gate, thereby making a contact to a wiring part formed in a self-aligning manner.
Further, Japanese Unexamined Patent Application Publication No. 2006-49737 (Patent Document 3) discloses a memory cell in which a memory gate line has a contact part formed on a sidewall of a selection gate line via an insulating film and extending over from a second part of the selection gate line to a device isolation region in the X direction, and is connected to a wiring via a plug embedded in a contact hole formed in the contact part.
Furthermore, Japanese Unexamined Patent Application Publication No. 2005-347679 (Patent Document 4) discloses a method in which, when a silicon oxide film covering a memory cell selection MISFET is subjected to etching to form connection holes which reach a source and a drain in a manufacturing process of a DRAM, a silicon nitride film is formed on an upper part and a sidewall of a gate electrode of the memory cell selection MISFET, thereby forming the connection holes in a self-aligning manner.